The multi-platen design takes wafers through a sequence of different process steps that polish the wafer with different slurries at different rates as it moves between polishing platens. After barrier, seed and copper fill layers are deposited in the interconnect structures, CMP is used to remove excess film from the wafer, leaving a smooth, flattened surface for building subsequent circuit layers. This system is used for planarizing devices at 0.25 micron and below geometries.Ĭopper CMP is the final step in the dual damascene copper process flow. The Mirra Electra CMP system advances the industry's ability to implement dual damascene copper interconnect technology for high-speed semiconductor chips by enabling high-precision removal and planarization of copper and barrier films.
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